• Energy Research

Severe silicon lifetime degradation was found after its high-temperature treatment in III–V material growth chambers for the fabrication of III–V/Si multijunction solar cells. Further improvement of the cell efficiency requires insights into the root cause of such lifetime degradation and how to protect the silicon lifetime accordingly. While the exact origins of such degradation remain largely unknown, most published work concluded that extrinsic impurities that diffuse into the silicon bulk during the thermal treatment are the sole reason. In this article, we show that while not necessarily present in every float-zone silicon wafer, grown-in defects that can be thermally activated is also a key mechanism behind the observed silicon lifetime degradation during anneal in our molecular beam epitaxy chamber. As such, annealing of the silicon wafer in the furnace at 1000 °C to annihilate the grown-in defects, together with the deposition of a SiNX diffusion barrier to prevent the extrinsic impurities from diffusing into the silicon bulk, are both required to preserve the silicon lifetime throughout the III–V material growth steps.

Results for a room temperature contacting method applied to the p -type rear surface of monocrystalline and multicrystalline solar cell structures are presented. Monocrystalline silicon devices with the rear contacts prepared using the point contacting by localized dielectric breakdown method are reported with an efficiency of 19.2%. The devices show improved measurements of key performance metrics of ρc of 1.6 ± 0.8 mΩcm2 and J 0 c of 2100 ± 650 fAcm−2. This contacting approach is also demonstrated for multicrystalline silicon cells, with no evidence of parasitic breakdown at grain boundary sites. The multicrystalline device implementation highlights a key advantage of this contacting method, namely a relatively free choice of annealing temperature. This flexibility allows process optimization such that the activation of light-and-elevated-temperature-induced degradation is prevented in hydrogenated multicrystalline silicon, while still maximizing the benefits to bulk lifetime.

Abstract A 2-terminal, dual-junction, epitaxially integrated, GaAsP/Si tandem solar cell with an 3rd party certified efficiency of 23.4 % was fabricated via MOCVD growth on an ex-situ produced Si sub cell. The drastic efficiency improvement over the authors previous peer-reviewed demonstration of such a device architecture is examined. Critical advancements in top cell design to maximize short wavelength response were critical in enabling improved top cell response. An in-depth analysis of this champion tandem cell has identified key loss mechanisms which elucidate the pathway for further efficiency gains. First, voltage dependent collection efficiency in the GaAsP top cell is the primary cause of fill factor losses currently limiting efficiency. Analysis of spectrally resolved I–V measurements and analytical device modeling and indicate poor diffusion length due to elevated dislocation densities as the likely cause for the voltage dependent collection efficiency. Second, modeling for the GaAs0.75P0.25 top cell, using experimental data at multiple dislocation densities, provides quantitative understanding of the current and voltage losses associated with threading dislocations providing a clear efficiency pathway with reduction in dislocation density. Lastly Si subcell modeling identifies the pathway for further Si subcell advances over the present, simplistic design, which has yet to employ the known benefits of rear surface texture or dielectric passivation.