The EUPEX consortium aims to design, build, and validate the first EU platform for HPC, covering end-to-end the spectrum of required technologies with European assets: from the architecture, processor, system software, development tools to the applications. The EUPEX prototype will be designed to be open, scalable and flexible, including the modular OpenSequana-compliant platform and the corresponding HPC software ecosystem for the Modular Supercomputing Architecture. Scientifically, EUPEX is a vehicle to prepare HPC, AI, and Big Data processing communities for upcoming European Exascale systems and technologies. The hardware platform is sized to be large enough for relevant application preparation and scalability forecast, and a proof of concept for a modular architecture relying on European technologies in general and on European Processor Technology (EPI) in particular. In this context, a strong emphasis is put on the system software stack and the applications. Being the first of its kind, EUPEX sets the ambitious challenge of gathering, distilling and integrating European technologies that the scientific and industrial partners use to build a production-grade prototype. EUPEX will lay the foundations for Europe's future digital sovereignty. It has the potential for the creation of a sustainable European scientific and industrial HPC ecosystem and should stimulate science and technology more than any national strategy (for numerical simulation, machine learning and AI, Big Data processing). The EUPEX consortium – constituted of key actors on the European HPC scene – has the capacity and the will to provide a fundamental contribution to the consolidation of European supercomputing ecosystem. EUPEX aims to directly support an emerging and vibrant European entrepreneurial ecosystem in AI and Big Data processing that will leverage HPC as a main enabling technology.

HPC Digital Autonomy with RISC-V in EurHPC Digital Autonomy with RISC-V in Europe (DARE) will address Europe’s deficit in digital autonomy for High Performance Computing and AI, by creating truly European products for European supercomputers for research and industry. The project builds upon the solid research foundation from EPI, EUPILOT, EUPEX, DEEP-SEA, eProcessor, MEEP and related projects, and it takes advantage of the open RISC-V ecosystem, chiplet revolution and open-source software. It is the first phase of the ambitious 6-year plan set out in the DARE FPA proposal, and it defines clear intra- and inter-phase SMART KPIs and success criteria, on the road to European digital autonomy while supporting current and future computing needs. We will develop and tape-out, in advanced technology, three RISC-V-based chiplets: a vector accelerator for high-precision HPC and emerging applications, an AI Processing Unit inference accelerator for HPC AI applications and an HPC-focused European general-purpose processor. These chiplets bring cost and yield advantages by going beyond the reticle size limitations imposed by monolithic chips and they will be integrated in a mix-and-match fashion to build specific systems. DARE uses a carefully selected set of the most significant European HPC and AI applications to drive hardware (HW) and software (SW) activities in a HW/SW co-design scheme, in order to ensure that the project’s HW and SW results meet the requirements of the European HPC and AI communities. It will build a complete SW stack, optimized for DARE HW, that supports these cutting-edge applications. To make rapid progress, SW and HW developments proceed in parallel, leveraging early access to RISC-V hardware emulation and simulation. Finally, the project will elaborate a detailed technical roadmap and pathfinding, defining the major steps and milestones to be followed in the next phase, in order to achieve the goal of next-generation post-exascale EU supercomputers.

SEANERGYS creates an integrated European software solution that optimises the operation of supercomputers. In doing so, it addresses four different objectives: reducing the amount of energy used for real-world workload mixes as the primary objective, optimising resource utilisation, enhancing system throughput and reducing response time as secondary objectives. Since these objectives can conflict with each other, site-specific policies define the weights attached to each, and the SEANERGYS SW suite will tailor system operation towards the combined optimum. Possible scenarios include improving the throughput of HPC systems, generating more R&D results for a given energy budget, or produce a fixed set of R&D results with less energy, while striving to keep response times constant. The solution consists of a comprehensive monitoring infrastructure (CMI), an Artificial Intelligence data analytics system (AIDAS), and a dynamic scheduling and resource management system (DSRM). The CMI gathers data from hardware and software sensors, and correlates it with scheduler information to identify jobs that do not fully utilize allocated resources. Users receive automatic feedback on energy and resource use for each run, plus information on how to optimize these. The DAIS leverages AI models trained with a vast set of operational data of the participating HPC sites. It fingerprints resource usage patterns, predicts future job behaviour, and identifies complementary job profiles for potential co-scheduling. Finally, the DSRM utilizes these insights to develop scheduling policies that maximize resource utilization and energy efficiency, and supports jobs/applications with dynamic and adaptable resource profiles. The SEANERGYS solution will be ready for deployment up to Exascale level. To ensure production-quality, the project builds on results from European projects, the competency of well-established research groups and companies, and widely used open-source codes. These are input for an integrated software system that achieves the functionality, performance and stability needed by European HPC centres, defined by KPIs and acceptance criteria and processes established at the project start. An agile, professional software development method will leverage a modern DevOps framework and strive to provide end-to-end traceability by linking and tracking requirements, interface, functional and performance specifications, code design and development steps, and validation/verification throughout the development lifecycle. Validation/verification measures will include code reviews, automated SW quality analysis, unit and integration tests and a verification suite. The project will implement a staged testing and validation process, with functionality tests on single-nodes, scaling tests on mid-sized platforms, and finally acceptance tests on production supercomputers.

The HPC Digital Autonomy with RISC-V in Europe (DARE) will invigorate the continent’s High Performance Computing ecosystem by bringing together the technology producers and consumers, developing a RISC-V ecosystem that supports the current and future computing needs, while at the same time enabling European Digital Autonomy. DARE takes a customer-first approach (HPC Centres & Industry) to guide the full stack research and development. DARE leverages a co-design software/hardware approach based on critical HPC applications identified by partners from research, academia, and industry to forge the resulting computing solutions. These computing solutions range from general purpose processors to several accelerators, all utilizing the RISC-V ecosystem and emerging chiplet ecosystem to reduce costs and enable scale. The DARE program defines the full lifecycle from requirements to deployment, with the computing solutions validated by hosting entities, providing the path for European technology from prototype to production systems. The six year time horizon is split into two phases, enabling a DARE plan of action and set of roadmaps to provide the essential ingredients to develop and procure EU Supercomputers in the third phase. DARE defines SMART KPIs for the hardware and software developments in each phase, which act as gateways to unlock the next phase of development. The DARE HPC roadmaps (a living document) are used by the DARE Collaboration Council to maximize exploitation and spillover across all European RISC-V projects. DARE addresses the European HPC market failure by including partners with different levels of HPC maturity with the goal of growing a vibrant European HPC supply chain. DARE Consortium partners have been selected based on the ability to contribute to the DARE value chain, from HPC Users, helping to define all the requirements, to all parts of the hardware development, software development, system integration and subsequent commercialization.