The challenges and major HiCONNECTS objectives are to transform the centralized cloud platform to decentralized platforms which include edge cloud computing in a sustainable, energy-efficient way. This will bring cloud services including Artificial Intelligence (AI) closer to the IOT end-users, which enables them to really use the COT and IOT efficiently. The technologies underpinning this revolutionary step include the development of high-performance computing, storage infrastructure, network interfaces and connecting media , and the analysis of IOT sensors and big data in real-time. This major step forward will enable, for example, the mobile clients (during the 5G deployment phase and 6G exploration) to move among different places with minimum cost, short response time and with stable connection between cloud nodes and mobile devices. The main underlying technology to be developed by the HiCONNECTS consortium, comprising large industrial players, universities and RTOs, and many SMEs, can be summarized under the title: heterogenous integration (HI) which is needed to meet the computing power, bandwidth, latency and sensing requirements for the next generation cloud and edge computing and applications. The HI revolution brings the electronic components and systems (ECS) into a new domain, which combines traditional silicon wafers integrated circuit (IC), InP based high speed electronics , and Si and InP photonics devices and interconnect. The HiCONNECTS ambition is to demonstrate, through HI development, a leap in computing and networking reliability and performances across the full vertical and horizontal ECS value chain (i.e. essential capabilities and key applications) in a sustainable way. In addition, HiCONNECTS will focus on the development of next generation design, algorithms, equipment (HW/SW), systems and Systems of Systems (SOS).

The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.