The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials

The BASMATI project will address the development of active nanomaterial and electrochemical inks for printing technologies such as screen and inkjet printing. The ink formulations will be tested on a case study through printing of a thin film battery. The general objective of the project is to scale-up the ink formulations to pilot line ensuring large volume fabrication of new products with improved properties for printing application. Especially, the particles definition at nanometer size will be one key parameter for the compatibility in ink jet printing. Moreover, knowledge will also be generated on electrochemical inks formulation and additives used in order to stabilize the ink products. The concept of nanomaterials for printing application will be applied to flexible printed electronics and more specifically to printed batteries. These printed batteries are needed as power source at the closest part and the development of printed electronics so as to as to design an all-in-one product allowing better process ability in ink jet process for 3D design and 2D screen printing process. BASMATI will also provide a new source of nanomaterials for the formulation of conductive and electrochemical inks. These nanomaterials will be metallic particle (Ni, Cu, Al) that will be usable for numerous applications of printed electronic on flexible substrate. Another type of nanomaterials will be layered positive active material such as LiNi1/3Mn1/3Co1/3O2 (NMC) and olivine LiFePO4 (LFP). The know-how level reached in BASMATI by research groups and transfer and up-scale to pilots (TRL 6) at SMEs and industry facilities will pave the way for future industrialization of inks formulations production for mass markets such as printed electronics. The compatible formulations in high throughput technologies will ensure a reproducible and reliable process for sophisticated fully digital micro-structured devices. Nanosafety will also be carefully considered in BASMATI project.

14ACMOS is about enabling manufacture of 14A Semiconductor technology. It addresses the 4 key pillars in IC technology development for manufacture; Lithography, Metrology, Mask Infrastructure and Process technology. Carl ZEISS, Trumpf and ASML are the main parties to push the lithography solutions to 14A. Between Carl ZEISS, Fraunhofer, RWTH, UW and TNO further understanding of optics life time and plasma physics is pursued in optimizing optics transmission and lifetime. Nova, BRT, ILT and PTB address measurement sensitivity enhancement of X-ray and optical based methodologies to meet the 14A requirements. Imec, TNO, PTB, UPB and RWTH will combine and tune metrology techniques specifically for the assessment of EUV reticle degradation. On throughput and resolution enhancement Bruker, EXC, PTB and AMIL will work on X-ray sources and AMIL, ICT and NFI on e-beam and SPM platforms for in-line metrology. On the reduction of Total Measurement Uncertainty, Prodrive and AMIL cover the development of an ultra-high precision wafer stage and NVIDIA, AMIL and Prodrive the development of a next generation image processing system. In Mask Infrastructure there are FHG (IISB), ASML, Carl Zeiss covering the creation of a simulation based mask repair strategy and with Carl ZEISS, ASML, PI and UPB HW/SW and process technology for particle removal is created and repair durability is covered with Carl ZEISS, ASML, Suss and UPB. Process technology covers the creation of patterning solutions with the involvement of imec and TEL. On active device selection there will be imec, Cadence, IBS, JSR, Recif and TEL with THERMO enabling advanced TEM characterization. Middle Of Line and Back End Of Line solution development is with imec, TEL, Solmates and Coventor for process modules and Cadence the interface with the design community. On Sustainable Semiconductor Technology and Systems there are imec, Recif and ThermoFisher covering sustainable material and processing alternatives.

In line with industry needs, Moore’s law, scaling in ITRS 2013, and ECSEL JU MASP 2017, the main objective of the TAPES3 project is to discover, develop and demonstrate lithographic, metrology, EUV mask technology, devices and process modules enabling 3nm node technology. This is planned with available EUV/NA 0.33 scanners, and with system design and integration of a new hyper NA EUV lithography tool to enable more single exposure patterning at 3nm to create complex integrated circuits. Process steps for 3D devices as alternative to the conventional FINFet will be explored for application in the 3nm node. The impact of the application of these so called 3D devices on circuit topology and logic design will be explored. During the development, specific challenges in metrology for the characterization of 3D devices will be assessed and metrology tools will be newly developed. The result will be demonstrated in the imec pilot line. The TAPES3 project relates to the ECSEL work program topic Equipment, Material and Manufacturing. It addresses and targets, as set out in MASP, the grand Challange of "More Moore Equipment and Materials for sub 10nm technologies" by exploring the requirements and solutions for the 3nm node. The project touches the core of the continuation of Moore’s law. Moreover, the cost aware development process will support the involved companies, and will place them in a preferred position over their worldwide competition. Through their worldwide affiliations, the impact of the TAPES3 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.

The ORCA Project proposal addresses topic GV-03-2016, of the Transport Work Programme. The work proposed will, in a single coordinated project, address all the aspects of the domain 2 “For pure and plug-in hybrids, power-train system integration and optimisation through the re-use of waste heat, advanced control, downsizing of ICEs, innovative transmissions and the integration of electronic components” regarding Heavy Duty Vehicles. The activity proposed will be conducted by an 11-member consortium from 7 different European Members States representing all requested competencies in the field of powertrain optimization for Heavy Duty vehicles. The consortium comprises OEMs with IVECO-ALTRA, CRF and VOLVO (also members of EUCAR, suppliers VALEO, BOSCH, JOHNSON MATTHEY and JSR MICRO (CLEPA), leading Engineering and Technology Companies/organizations and Universities with TNO, FRAUNHOFER, and VUB (EARPA). The majority are also active members of ERTRAC and EGVIA. The overall objectives of the ORCA project are: Reduce the TCO to the same diesel vehicle TCO level, targeting over 10% system cost premium reduction compared to actual IVECO hybrid bus and VOLVO conventional truck with the same performances, same functionalities and operative cost, and also targeting up to 10% rechargeable energy storage (RES) lifetime/energy throughput improvement. Improve the hybrid powertrain efficiency up to 5% compared to actual IVECO hybrid bus and conventional truck through optimized RES selection & sizing and by improving the energy and ICE management. Reduce the fuel consumption by 40% compared to an equivalent conventional HD vehicle (bus & truck). Downsize the ICE by at least 50% compared to actual IVECO hybrid bus and VOLVO conventional truck. Improve the electric range from 10km to 30km by adding the PHEV capabilities and optimising the RES capacity. Case study assessment to replace a diesel engine by a CNG engine for future heavy-duty vehicles.