The “Pilot Line for Micro-Transfer-Printing of Functional Components on Wafer Level” project (MICROPRINCE) is focused on creation of a pilot line for heterogeneous integration of smart systems by micro-transfer-printing (µTP) in a semiconductor foundry manufacturing environment. Functional components like processed III/V devices, optical filters, and special sensors will be transfer printed to demonstrate the capabilities of the technology and pilot line. Based on several EU and national research activities demonstrating successfully the feasibility of µTP technology in a scientific and laboratory environment, the MICROPRINCE consortium has the goal to setup the first worldwide open access foundry pilot line for heterogeneous integration by µTP and to demonstrate its capability on five defined target application scenarios. For this purpose, the consortium consisting of 13 partners from four different countries combine their expertise along the value chain from materials and equipment, technology and semiconductor processing, integrated circuit and system design, test and application. The partners are industrial companies incl. SME’s, accompanied by leading research institutes with a clear focus on production and application in Europe. The working principle of the micro-transfer-printing technology is to use a micro-structured elastomer stamp to transfer microscale functional components from their native substrates onto non-native substrates. The lateral dimensions of the functional components can range from a few microns to a few hundreds of microns with thicknesses of only a few microns. The native substrate contains the functional components to be printed and is flexible in size and material. The MICROPRINCE pilot line is acting as a regional and nationwide competence cluster for a novel technology with European dimensions for heterogeneous system integration and supports the ECS industry to reach leadership in key applications.

The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt. The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the support technology to demonstrate the high performances path as well as the robustness of the ePCM solution. The next generation of FDSOI ePCM will be main path for general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security. On top of the development and industrialization of silicon process lines and SoC design, storAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.

The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform. Additional developments will be performed for the integration of memory, power management, connectivity, hard security on the same chip. The project will also target the industrialization of the embedded Phase Change Memory (PCM) technology built on top of the FDSOI 28nm logic process pilot line. The development of the ePCM will be driven by the final application requirements as well as decreasing the power consumption. The alternative memory solutions will be also studied as they have different - and complementary - traits in such areas as read/write speed, power and energy consumption, retention and endurance, and device density and benchmarked with the ePCM and the conventional eFlash. Continued advances in materials, device physics, architectures and design could further reduce the energy consumption of these memories. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage. These activities encompass such developments as: technology enhancements for various specific application requirements such as wide temperature range and reliability, high security requests, high flexibility…, design enablment allowing first time silicon success, prototyping demonstrator products in the different application areas. In the WAKEMEUP project, new devices and systems will be developed by the application partners in automotive and secure based on FD-SOI and embedded digital technology to answer specific applications needs.