The metrology domain (which could be considered as the ‘eyes and ears’ for both R&D&I and production) is a key enabler for productivity enhancements in many industries across the electronic components and system (ECS) value chain and have to be an integral part of any Cyber Physical Systems (CPS) which consist of metrology equipment, virtual metrology or Industrial internet of things (IIoT) sensors, edge and high-performance computing (HPC). The requirements from the metrology is to support ALL process steps toward the final product. However, for any given ECS technology, there is a significant trade-off between the metrology sensitivity, precision and accuracy to its productivity. MADEin4 address this deficiency by focusing on two productivity boosters which are independent from the sensitivity, precision and accuracy requirements: • Productivity booster 1: High throughput, next generation metrology and inspection tools development for the nanoelectronics industry (all nodes down to 5nm). This booster will be developed by the metrology equipment’s manufacturers and demonstrated in an industry 4.0 pilot line at imec and address the ECS equipment, materials and manufacturing major challenges (MASP Chapter 15, major challenges 1 – 3). • Productivity booster 2: CPS development which combines Machine Learning (ML) of design (EDA) and metrology data for predictive diagnostics of the process and tools performances predictive diagnostics of the process and tools performances (predictive yield and tools performance). This booster will be developed and demonstrated in an industry 4.0 pilot line at imec, for the 5nm node, by the EDA, computing and metrology partners (MASP Chapter 15, major challenge 4). The same CPS concept will be demonstrated for the ‘digital industries’ two major challenges of the nanoelectronics (all nodes down to 5nm) and automotive end user’s partners (MASP Chapter 9, major challenges 1and 3).

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7’s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.

The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt. The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the support technology to demonstrate the high performances path as well as the robustness of the ePCM solution. The next generation of FDSOI ePCM will be main path for general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security. On top of the development and industrialization of silicon process lines and SoC design, storAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.