The tremendous increasing of data collection, analysis, storage and processing has raised concerns towards the optimization and rethinking of the edge-computing paradigm. Indeed, moving the data analysis and processing closer to the location where the data is collected and eventually stored, is the only way to achieve realistic, green and sustainable ICT. It is foreseen that the ITC market, which already consumes 11% of the world electricity, should be multiplied by 2030 by 2 to 5. Three key points have been identified to allow a massive reduction of the power consumption in complex systems: i) drastically reducing the power consumption of the memory hierarchy by replacing some of its parts by emerging fast and non-volatiles technologies (to reduce the leakage). ii) Rethinking the computing schemes to go beyond standard CMOS approach, by taking advantage of emerging non-volatile devices to intrinsically mix memory and logic. iii) Using emerging non-volatile devices to implement very efficient neuromorphic accelerators for specific tasks usually performed by GPUs. Among these emerging technologies, spintronics offers high speed, non volatility and endurance, but the energy cost of magnetization switching remains high. The SPINTEC laboratory discovered in 2020-2021 that it is possible to control spin currents using ferroelectricity rather than ferromagnetism, which leads to a huge reduction of the writing power consumption. The aim of this project is to explore novel functionalities offered by this new technology, from a design integration perspective. Using our understanding of the spin transport in these devices and our expertise about design of hybrid circuits embedding emerging devices, we will investigate the benefits of its use in memory, logic and neuromorphic computing for ultra-low power and energy efficient systems.

We will develop digitally compatible, low-barrier magnetic tunnel junctions (MTJs), hybrid measurement and control circuits, and architectures to use their natural stochasticity in the context of various biologically inspired probabilistic computational models. This work is motivated by research in the neuroscience community highlighting the inherently stochastic behavior of neural processes. Stochastic MTJs, implemented with small modifications to the commercial back-end-of-line (BEOL) integrated MTJ process, provide a natural substrate for computational models exploiting this randomness. Lowering the barrier close to room temperature puts devices in a superparamagnetic regime, where thermal fluctuations change the device state. We will design and test both rate coded and temporally coded stochastic circuit primitives. Building on experiments, we will design probabilistic computing architectures such as energy-based machine learning models, non-equilibrium oscillatory models, and time-of-arrival based temporal models. Leveraging the cross-stack expertise of our team from material growth and device fabrication to VLSI design and computer architecture, we will bridge the gap between these domains by developing computing abstractions that are informed by the practical challenges of next-generation technology integration while being guided by applications that can make the most of such randomness effectively. Keywords: Magnetic tunnel junctions; Spintronic-CMOS circuits; Markov models; Probabilistic computing; Stochastic devices; Temporal Computing. Our project follows the grand neuroscientific challenge of reverse-engineering the brain into technological development. We start with the idea that the probabilistic nature of the brain may be fundamental to its computational ability as postulated by researchers, based on the stochastic nature of basic neural processes such as synaptic release. The path from biology to technology involves diverse fields such as mathematics, electrical engineering, computer science, material science, physics, and neuroscience. We will build and test circuit primitives that convert the inherent randomness of superparamagnetic MTJs (SMTJs) into usable encoding schemes. We will then utilize these primitives as building blocks of architectures that are energy-efficient, reliable, and robust to variations by design. The possibility of straightforward integration of our magnetic-tunnel junction-based circuits into commercial fabrication raises the possibility of large scale networks of coupled stochastic devices as a substrate for subsequent investigations into physics, network computation, and neural processes operating on the edge of chaos. The results of this research will advance knowledge and understanding in the area of emerging technologies for novel computing. The design of digitally interfaced, tunable, and energy-efficient stochastic unit cells will enable the compact physical realization of complex networks exhibiting little-explored non-equilibrium dynamics and unique stochastic temporal behavior. This understanding will be important for the development of low power, distributed intelligence for edge computing where low energy optimization and inference is important. We will disseminate the scientific advances from this research to the public through a variety of avenues such as lab tours for students, parents, government staff, and science journalists. We will conduct seminars at the University of Maryland and CEA (SPINTEC), as well as produce pedagogical YouTube videos in English, French, and Spanish describing our work. Additionally, we will collaborate with institutional summer internship programs that foster a research mindset in high school and undergraduate students to increase participation from the local community. Exposure to diverse scientific topics and international collaborations will be very beneficial to researchers, graduate students, and postdocs hired with requested funds.

The growing deployment of connected devices in Edge Computing involves the development of protection schemes to guarantee the security requirements concerning the data privacy and the software execution integrity. Among all solutions, implementing non-volatile (NV) technology in processors should allow the development of recovery mechanisms that enhance system resilience against potential attacks. However, this NV capability also used for power management, implying backup/restore strategy, raises a question: "Do the additional mechanisms introduce new vulnerabilities?" The SCREAM project aims to develop a RISC-V architecture with NV MRAM memory elements while ensuring compliance with security requirements. It will address 3 challenges: 1) the characterization of vulnerabilities of backup/restore mechanisms in NV processor, 2) the modeling of an innovative Voltage Gated Spin Orbit Torque (VG-SOT) MRAM cell as elementary cell to build blocks as register and memory and 3) the design of countermeasures from these blocks to mitigate hardware attacks. To reach these objectives, SCREAM will be organized in three main work packages. Firstly, the specification and the design of NV RISC-V processor architecture. Secondly, the evaluation of security advances taking profit of MRAM blocks. Thirdly, the definition of mitigation mechanisms as protection schemes at cell level, hardware level and software level. Given these parameters, the SCREAM project endeavors to pioneer a secure, non-volatile computing paradigm through innovative MRAM integration, addressing critical vulnerabilities and advancing protection mechanisms, thereby setting a new standard for secure edge computing architectures.

Magnetic Random Access Memory (MRAM) is now available on the market, with applications such as in FPGA, or as stand-alone cache memories. The concept of Perpendicular-Shape-Anisotropy (PSA) MRAM has been made to enhance the market of MRAM, in which the usual ultrathin spintronic storage layer is replaced with a vertical magnetic pillar, allowing to sustain retention at <10nm size and elevated temperature. Now that its read-write proof of concept has been made, M-bed-RAM’s objective is to address the fundamental bottlenecks preventing its technological uptake, related to dense fabrication and low-current writability. We propose three concepts to globally solve this: dense fabrication by embedding the element in vias; use graded-anisotropy pillars to ease writability; implement synthetic antiferromagnet core-shell elements, addressing both writability and density by a shielding effect. Practical work consists of simulation to optimize the design; optimization or development of atomic layer deposition 3d spintronic material and stacks for 3D conformality; synthesis and magnetic qualification of stand-along storage layer pillars; the proof-of-concept or read/write operation. The consortium brings complementary expertise: nanowire and MRAM, micromagnetic simulation, clean-room technology, advanced magnetic microscopy and electric testing (SPINTEC), electroplating of magnetic materials to fill the vias (NEEL), thin-film ALD spintronic materials for conformal deposition and produce core-shell structures (IJL). Success of the project should open new markets for MRAM, fueling the European chip act with innovative capacities. More broadly, this will provide knowledge and technology suitable to implement other spintronic concepts in a 3D architecture in the future, e.g., for logic or artificial intelligence purposes.

In spintronics, the spin dependent transport properties of ferromagnetic (F) materials lie at the heart of devices working principles. Conversely, antiferromagnetic (AF) materials are so far used for their magnetic properties only. However, spin dependent transport with AF materials is of high interest: spin absorption lengths are expected to be longer in AF than in F materials. This, together with the fact that AF materials show no stray fields, would permit lower power consumption and ultimate downsize scalability. The aim of this ‘Jeune Chercheuse – Jeune Chercheur’ (JCJC) project is the study of spin dependent transport with AF materials (spin penetration depth, spin mixing conductances, spin absorption mechanisms, spin Hall angle; and subsequent spin transfer and spin-orbit torques) in order to pave the way and set the fundamental foundations towards AF-spintronics.