The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.

The overall objective of the IT2 project is to explore, develop and demonstrate technology options that are needed to realize 2nm CMOS logic technology extending the scaled Semiconductor technology roadmap to the next node in accordance to Moore’s law. These activities cover creation of Lithography equipment, new Processes & Modules and Metrology tools capable to create and deal with new 2nm node 3D structures, defect analysis, overlay and features. The topics addressed by the program relate to the ECSEL MASP 2019 Chapter 10; “Process Technology, Equipment, Materials and Manufacturing for electronic components and systems”, with emphasis on the following major challenge “the Extension of world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and “Developing Technology for heterogeneous System-on-Chip (SoC) Integration” of the ECSEL JU Annual Work Plan 2019. The relation of the IT2 project to world leadership regards the extension of the scaled semiconductor technology roadmaps and thereby maintain competence in advanced More Moore technology in Europe to support leading edge manufacturing. The relation of the IT2 project to the Developing Technology for heterogeneous System-on-chip Integration comes from activities regarding “System Scaling” in which technology is developed that enables wafer-to-wafer bonding creating 3D heterogeneous solutions with the aim to resolve performance limitations in power and data congestion. In regard to the annual work plan 2019, the IT2 project support the ECSEL JU objectives by contribution to the development of a strong and competitive Electronic Components and Systems (ECS) by involving many of the equipment and tool developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KLA along the value chain and knowledge institutes such as ARCNL, imec, PTB, TNO and TU/e. And by stimulating a dynamic ecosystem through through the involvement of SMEs like IBS, Recif, Reden and Unity.

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved. To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line. The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025. This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the “PC era” to 10 billion in the “Mobile + cloud era” to the future “Intelligence era” in which there will be over 100 billion intelligent connected devices. To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moore’s Law and will continue to do so. The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.