HPC Digital Autonomy with RISC-V in EurHPC Digital Autonomy with RISC-V in Europe (DARE) will address Europe’s deficit in digital autonomy for High Performance Computing and AI, by creating truly European products for European supercomputers for research and industry. The project builds upon the solid research foundation from EPI, EUPILOT, EUPEX, DEEP-SEA, eProcessor, MEEP and related projects, and it takes advantage of the open RISC-V ecosystem, chiplet revolution and open-source software. It is the first phase of the ambitious 6-year plan set out in the DARE FPA proposal, and it defines clear intra- and inter-phase SMART KPIs and success criteria, on the road to European digital autonomy while supporting current and future computing needs. We will develop and tape-out, in advanced technology, three RISC-V-based chiplets: a vector accelerator for high-precision HPC and emerging applications, an AI Processing Unit inference accelerator for HPC AI applications and an HPC-focused European general-purpose processor. These chiplets bring cost and yield advantages by going beyond the reticle size limitations imposed by monolithic chips and they will be integrated in a mix-and-match fashion to build specific systems. DARE uses a carefully selected set of the most significant European HPC and AI applications to drive hardware (HW) and software (SW) activities in a HW/SW co-design scheme, in order to ensure that the project’s HW and SW results meet the requirements of the European HPC and AI communities. It will build a complete SW stack, optimized for DARE HW, that supports these cutting-edge applications. To make rapid progress, SW and HW developments proceed in parallel, leveraging early access to RISC-V hardware emulation and simulation. Finally, the project will elaborate a detailed technical roadmap and pathfinding, defining the major steps and milestones to be followed in the next phase, in order to achieve the goal of next-generation post-exascale EU supercomputers.

Our solution is a hardware (HW) and software (SW) platform optimized for inference at the edge, which, as a market, is projected to grow exponentially, and to reach €15.52 B in 2025. Our solution will accelerate the latest generation of neural network models for computer vision, natural language processing and generative AI to revolutionize the way we use AI, at a fraction of the costs and power consumption of available solutions. The HW will be available in various form factors for rapid adoption and is highly scalable–from a single device running in an embedded system to multiple instances on cards in an edge datacenter. Our SW tools provide a consistent, powerful and easy-to-use development environment for all of these instances, while driving the adoption of AI through our no-code web composer. We have a strong team led by the CEO who was the Head of Artificial Intelligence at Bitfury and has 20+ years of managerial experience in tech corporations such as Asus and Advantech.

Axelera-FAST (Fueling Axelera’s Semiconductor & AI Transformation) is a scale-up project designed to scale Axelera AI up and mass-produce Europe’s first fully sovereign AI acceleration platform. As AI demand surges, Europe imports 90% of its AI chips, creating a critical vulnerability. Our project will eliminate this dependency by expanding our Digital In-Memory Computing (DIMC) and RISC-V-based AI processors, which deliver 10x faster performance and 3-5x better energy efficiency than GPUs repurposed for AI. To date, Axelera AI has raised €173 in funding, innovation loans and grants, and grown to 200+ employees across 15 countries, and built a 200+-person team across 15 countries. We have developed three AI chips, with over 120 customers integrating them into retail automation, robotics, and security. The next step is mass production, scaling into High-Performance Computing (HPC), and ensuring Europe’s AI sovereignty. However, scaling AI hardware is capital-intensive, requiring substantial investment in chip fabrication, supply chain resilience, and market expansion. Without EU support, Europe risks long-term dependency on non-EU suppliers, threatening its digital infrastructure and economic competitiveness. EIC funding is critical to accelerate production, advance R&D, and establish a sustainable AI ecosystem. With EU STEP funding, Axelera AI will secure Europe’s place in the AI revolution, eliminate reliance on foreign chips, and build a competitive, sovereign AI industry.

The HPC Digital Autonomy with RISC-V in Europe (DARE) will invigorate the continent’s High Performance Computing ecosystem by bringing together the technology producers and consumers, developing a RISC-V ecosystem that supports the current and future computing needs, while at the same time enabling European Digital Autonomy. DARE takes a customer-first approach (HPC Centres & Industry) to guide the full stack research and development. DARE leverages a co-design software/hardware approach based on critical HPC applications identified by partners from research, academia, and industry to forge the resulting computing solutions. These computing solutions range from general purpose processors to several accelerators, all utilizing the RISC-V ecosystem and emerging chiplet ecosystem to reduce costs and enable scale. The DARE program defines the full lifecycle from requirements to deployment, with the computing solutions validated by hosting entities, providing the path for European technology from prototype to production systems. The six year time horizon is split into two phases, enabling a DARE plan of action and set of roadmaps to provide the essential ingredients to develop and procure EU Supercomputers in the third phase. DARE defines SMART KPIs for the hardware and software developments in each phase, which act as gateways to unlock the next phase of development. The DARE HPC roadmaps (a living document) are used by the DARE Collaboration Council to maximize exploitation and spillover across all European RISC-V projects. DARE addresses the European HPC market failure by including partners with different levels of HPC maturity with the goal of growing a vibrant European HPC supply chain. DARE Consortium partners have been selected based on the ability to contribute to the DARE value chain, from HPC Users, helping to define all the requirements, to all parts of the hardware development, software development, system integration and subsequent commercialization.

Electrification and autonomy drive the rapid evolution of modern vehicles, requiring increasing computational capabilities, coupled with safety and efficiency. The classical, decentralized multi- Electronic Control Units (ECU) architecture has significant drawbacks when it comes to scalability, and it is becoming untenable. The dominant megatrend pushes for an increasing number of key functionalities to be software-defined, with the direct implication that the software content (lines-of-code) in a vehicle will grow by 10x in just 5 years, to 1 billion by 2030. From a hardware viewpoint, increased complexity and autonomy requires a more centralized approach to on-board computing to curtail cost, latency and bandwidth bottlenecks of the in-vehicle network. Centralizing the E/E architecture requires merging multiple Electronic Control Units (ECUs) into powerful, fully programmable Domain Control Units (DCUs) or Zonal Control Units (ZCUs). To address this paradigm shift, the Rigoletto project will establish the foundation for a next-generation Automotive Hardware Platform based on the open RISC-V instruction set architecture (ISA), bolstering and securing Europe's leading role in the automotive electronics industry. The project aligns with the high-level goal of EU Chips Joint Undertaking and the of the industry-led Vehicle of the Future initiative: namely, the creation of a RISC-V based automotive hardware platform strongly linked with the formation of an open, software-defined vehicle ecosystem led by European automotive manufacturers and suppliers. Rigoletto aims at developing RISC-V intellectual property (IP) components, including processor cores, accelerators, interconnects, memory hierarchy and peripheral subsystems. A wide range of performance profiles will be targeted for next-generation DCUs and ZCUs, to enable increasingly electrified, automated, and connected vehicles.