The TAKE5 project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 10nm technology node and the ECSEL JU project SeNaTe aiming at the 7nm technology node. The main objective of the TAKE5 project is the demonstration of 5nm patterning in line with the industry needs and the ITRS roadmap in the Advanced Patterning Center at the imec pilot line using innovative design and technology co-optimization, layout and device architecture exploration, and comprising demonstration of a lithographic platform for EUV technology, advanced process and holistic metrology platforms and new materials. A lithography scanner will be developed based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules new materials will need to be introduced. Introduction of these new materials brings challenges for all involved deposition processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch steps will be studied. The project will be dedicated to find the best options for patterning. The project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary and covers all aspects of 5nm patterning development.

The SILENSE project will focus on using smart acoustic technologies and ultrasound in particular for Human Machine- and Machine to Machine Interfaces. Acoustic technologies have the main advantage of a much simpler, smaller, cheaper and easier to integrate transducer. The ambition of this project is to develop and improve acoustic technologies beyond state-of-the-art and extend its application beyond the mobile domain to Smart Home & Buildings and Automotive domains. In this project, it will be proven that acoustics can be used as a touchless activation and control mechanism, by improvement or development of different smart acoustic technology blocks (hardware, software and system level) and integrate these blocks at system level. At technology level, the SILENSE project will: - Adapt and improve cost, performance, directivity and power consumption of (MEMS) acoustic transducers (incl. testing and qualification) - Heterogeneously integrate arrays of acoustic transducers with other electronics, using advanced (3D) packaging concepts - Develop smart algorithms for acoustical sensing, localization and communication - Combine voice and gesture control by means of the same transducer(s) At application level the SILENSE project will: - Apply acoustical sensing for touchless activation/control of mobile devices, wearables and, more in general, IoT nodes. The project links to Smart Systems Integration (B4), and refers also to application application-related topics, such as Smart Mobility and Smart Society. The application scope of the developed technologies is broader and comprises more societal domains, such as smart home/buildings, smart factories (i.e. Smart Production) and even Smart Health. Furthermore, a clear cross reference with Semiconductor Process, Equipment and Materials (B1) is established in view of the heterogeneous integration of technology blocks. Conventional silicon technologies will be combined with printed (flexible, large area electronics).

The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials