This proposal describes the third core project of the Graphene Flagship. It forms the fourth phase of the FET flagship and is characterized by a continued transition towards higher technology readiness levels, without jeopardizing our strong commitment to fundamental research. Compared to the second core project, this phase includes a substantial increase in the market-motivated technological spearhead projects, which account for about 30% of the overall budget. The broader fundamental and applied research themes are pursued by 15 work packages and supported by four work packages on innovation, industrialization, dissemination and management. The consortium that is involved in this project includes over 150 academic and industrial partners in over 20 European countries.

The COSMICC consortium gathers key industrial and research partners with world-leading positions in the fields of Silicon photonics, CMOS electronics, Printed Circuit Board-Packaging, Optical transceivers and Data-Centers around a strong vision: mass commercialization of Si-photonics-based transceivers is possible starting in 2019 by enhancing the existing photonic integration platform of one of the partners, STMicroelectronics. COSMICC will develop optical transceivers that will be packaged on-board. Combining CMOS electronics and Si-photonics with innovative-high-throughput fiber-attachment techniques, the developed solutions are scalable to meet the future data-transmission requirements in data-centers and Super computing systems. With performances improved by an order of magnitude as compared with current VCSELs transceivers, COSMICC developed technology will answer tremendous market needs with a target cost per bit that the traditional WDM transceivers cannot meet. The early setting up of a new value chain will enable exploitation of the developed technologies. In a first high reward step-modification of the fabrication platform, COSMICC consortium will achieve mid-board optical transceivers in the [2Tbit/s -2pJ/bit- 0.2€ per Gbit/s]-class with ~200Gbit/s per fiber: the introduction of one process brick (SiN layer) in the photonic process will enable low-cost packaging techniques (up to 2x12 fiber channels) and practical coarse WDM implementation (4 wavelengths with no temperature-control requirements). The built demonstrators will be tested in lab and field environments. In compliancy with the enhanced-fabrication platform, lasers will be developed by heterogeneous integration of III-V material, targeting improved temperature behavior, and doubled-bit-rate payback. A second step-modification of the fabrication platform will consist in evaluating a disruptive process that enables SiGe layers with tunable Si-composition for achieving micrometer-scale devices.

This proposal describes the third stage of the EC-funded part of the Graphene Flagship. It builds upon the results achieved in the ramp-up phase (2013 - 2016) and the first core project (2016 - 2018), and covers the period April 2018 - March 2020. The progress of the flagship follows the general plans set out in the Framework Partnership Agreement, and the second core project represents an additional step towards higher technology and manufacturing readiness levels. The Flagship is built upon the concept of value chains, one of which is along the axis of materials-components-systems; the ramp-up phase placed substantial resources on the development of materials production technologies, the first core project moved to emphasise components, and the second core project will move further towards integrating components in larger systems. This evolution is manifested, e.g., in the introduction of six market-motivated spearhead projects during the Core 2 project.

The 2D Experimental Pilot Line (2D-EPL) project will establish a European ecosystem for prototype production of Graphene and Related Materials (GRM) based electronics, photonics and sensors. The project will cover the whole value chain including tool manufacturers, chemical and material providers and pilot lines to offer prototyping services to companies, research centers and academics. The 2D-EPL targets to the adoption of GRM integration by commercial semiconductor foundries and integrated device manufacturers through technology transfer and licensing. The project is built on two pillars. In Pillar 1, the 2D-EPL will offer prototyping services for 150 and 200 mm wafers, based on the current state of the art graphene device manufacturing and integration techniques. This will ensure external users and customers are served by the 2D-EPL early in the project and guarantees the inclusion of their input in the development of the final processes by providing the specifications on required device layouts, materials and device performances. In Pillar 2, the consortium will develop a fully automated process flow on 200 and 300 mm wafers, including the growth and vacuum transfer of single crystalline graphene and TMDCs. The knowledge gained in Pillar 2 will be transferred to Pillar 1 to continuously improve the baseline process provided by the 2D-EPL. To ensure sustainability of the 2D-EPL service after the project duration, integration with EUROPRACTICE consortium will be prepared. It provides for the European actors a platform to develop smart integrated systems, from advanced prototype design to small volume production. In addition, for the efficiency of the industrial exploitation, an Industrial Advisory Board consisting mainly of leading European semiconductor manufacturers and foundries will closely track and advise the progress of the 2D-EPL. This approach will enable European players to take the lead in this emerging field of technology.

Sustained 2-digit growth in internet traffic is raising the need for new photonic technologies enabling Petabit/s network capacities, whereas suppressed operator margins call for new concepts to make these networks more efficient. QAMeleon aims at a holistic solution towards scaling metro/core networks to the next decade. A new generation of SDN-programmable photonic components, modules and subsystems will be delivered, employing sliceability as a means of optimizing resource utilization and cutting operator costs by >30%. At the transponder side, QAMeleon will develop components for 2 generations ahead: Operating at 128 Gbaud, they will bring significant savings in footprint (>13×), energy/bit (10.4×) and cost/bit (>4.3×). At the ROADM side, QAMeleon will develop large-scale flex-grid wavelength-selective switches (1×24 WSS) and transponder aggregators (8×24 TPA), reducing footprint and cost/port by more than 40% and 28% respectively, with energy savings per ROADM node reaching 4×. Addressing the emerging needs of 5G network backhaul and datacenter interconnect (DCI) metro-access networks where dynamicity is pivotal, QAMeleon will develop an integrated flex-grid 1×4 WSS with nanosecond-scale switching time. The fast 1×4 WSS will be scalable to large channel counts (i.e. full C-band) and will enable savings in footprint, energy consumption and cost by 20×, 11.5× and 36% respectively. QAMeleon will integrate its innovative photonic components into functional subsystems: A 3 Tb/s sliceable bandwidth-variable transponder (S-BVT), a flexible ROADM with large-scale WSSs and TPAs, and a fast ROADM for metro-access. All necessary SDN software extensions, plugins and application interfaces will be developed, providing a complete functional SDN framework for the sliceable “white box” subsystems. QAMeleon’s devices will be integrated with the SDN software and validated in scalable demonstrators at Nokia’s lab infrastructure and on TIM’s deployed regional network fiber plant