The De-RISC project addresses computer systems within the space and aviation domains. De-RISC – Dependable Real-time Infrastructure for Safety-critical Computer – is a proposed project where an international consortium will introduce a hardware and software platform based around the RISC-V ISA. The work proposed in this project is to productize a multi-core RISC-V system-on-chip design already owned by CG and to port the XtratuM hypervisor owned by FEN to that design to create a full platform consisting of hardware and software for future European developments within space and aeronautical applications. De-RISC brings critical features to the market that make it unique in front of the competition: (1) No US export restrictions: most existing products use US technology, thus subject to US export control. De-RISC’s IP core platform and software will not be subject to any US regulatory influence by building on RISC-V. (2) Multi-core interference mitigation concepts by BSC integrated in the RISC-V SoC and validated by TRT become a unique feature, and will provide a key advantage w.r.t. competitors by limiting drastically interference while preserving high-performance operation. (3) Portability: The proposed development will create a RISC-V HW/SW platform that can be implemented in FPGAs and application specific standard products. This provides an edge for integrators that can adapt their choice of implementation technology based on mission requirements. (4) Fault-tolerance concepts: The platform will be provided by companies with experience in the space domain and with heritage in design of fault-tolerant systems. (5) Future-proof selection for new platforms: New software products are not being ported to SPARC and PowerPC architectures. With an established vendor providing a RISC-V platform there are guarantees of continued support for the hardware platform while developments from the commercial domain for the RISC-V architecture can be leveraged over time.

The DUROC project sets clear and measurable main objectives to reach a TRL 4 from TRL 2 as follows in 2 years: • Specifiy and design the next generation of ultra-programmable SoC (ULTRA7) taking benefit of leasson learnt from DAHLIA project (TRL 2) • Introduce the ARM 73 processor for very high performance processing specificly designed for advanced process node • Validate the SoC on a rad-hard demonstrator in 7nm FinFET technology from TSMC (TRL 4) • Validate reliability and radiation hardening performance of 7nm FinFET (TRL 4) • Propose a strategy and development plan up to flight model for the next ultra-reprogrammable SoC (ULTRA7) • Define the right approach for future SiP use in space applications At the end of the project, Europe will have all required technical information to be in a position to develop multiple components (SoC FPGA, ASIC etc) on 7nm FinFET which will be the most advanced process node for space. DUROC will bring Europe to an unprecedent leadership position in VLSI electronic for space. DUROC will be the first critial step to develop the next generation of ultra-reprogrammable SoC after NG-ULTRA. The ULTRA 7 will target the following objectives: • MPSoC ARM A73 64-bit processor scalability combining ARM R52 real-time control • More than 35 000 DMIPS (Millions Instructions per Second) • Radiation hardening reliability meeting space payload and platform applications requirements

Existing HW/SW platforms for safety-critical systems suffer from limited performance and/or from lack flexibility due to building on specific proprietary components, which jeopardize their wide deployment across domains. While some research attempts have been done to overcome some of these limitations, their degree of success has been low due to missing flexibility and extensibility, which would ensure that industry can take that path, as many industries need technologies on which they can rely during decades (e.g. avionics, space, automotive). A number of high-performance computing (HPC) commercial off-the-shelf (COTS) platforms offer the computation capabilities needed by autonomous systems in domains such as automotive, space, avionics, robotics and factory automation by means of multicores, GPUs and other accelerators. Unfortunately, the utilization of HPC platforms has been traditionally considered out of the reach of the safety critical systems industry due to the difficulties or roadblocks these platforms bring to the certification process. SELENE follows a radically new approach and proposes a Safety-critical Cognitive Computing Platform (CCP) with self-awareness, self-adapting, and autonomous capabilities. SELENE’s CCP uses artificial intelligence (AI) techniques to adapt the system to the particular internal and external (environmental) conditions with the aim of maximizing the efficiency of the system being able at the same time of meeting application requirements. AI techniques are feed with information provided by the on-line monitors and external sensors and are applied in a transparent way without compromising the safety of the system. To ensure safety requirements are preserved SELENE’s CCP relies on the strong isolation capabilities provided at hardware and software levels.