*What if we had software bots that tirelessly test, debug, and monitor our software systems?* IT workers are expensive and scarce. So why can't we further automate boring, repetitive activities such as testing and debugging? The problem is that we lack computer-readable _specifications_ (so-called _oracles_) for what the system should do or not do. For decades, this _oracle problem_ has been a roadblock to automated test generation, trusted software repairs, and accurate monitoring of software. Building on groundbreaking research to infer input languages of systems, S3 introduces a unified approach to _learning oracles automatically_. It takes a given software system; _infers_ and _decodes_ its inputs and outputs; and runs _experiments_ to extract _models_ of how the system behaves, capturing its semantics by predicting output features for given input features. These models, named _system invariants_, allow to _fully automate_ critical software development activities: TESTING. System invariants encode _languages_ for automatically generating test inputs and provide _oracles_ for checking test results: "In the TLS server, the in the must be the same as in the ." DEBUGGING. System invariants allow narrowing down causes of software behavior ("The X.509 public key certificate is not recognized if contains a zero byte"). Generated tests and oracles ensure reliable automated repair. MONITORING. System invariants enable detecting abnormal behavior at runtime ("In 'log4j', logging a containing '"${jndi:}"' opens "). Problematic queries can be isolated and investigated until the problem is fixed. In the future, testing, debugging, and monitoring would thus be taken over by _software bots_ who would autonomously explore software behavior, report issues, and suggest actions to their human co-workers, boosting developer productivity and software reliability.

Graph-theoretical models are natural tools for the description of road networks, circuits, communication networks, and abstract relations between objects, hence algorithmic graph problems appear in a wide range of computer science applications. As most of these problems are computationally hard in their full generality, research in graph algorithms, approximability, and parameterized complexity usually aims at identifying restricted variants and special cases, which are at the same time sufficiently general to be of practical relevance and sufficiently restricted to admit efficient algorithmic solutions. The goal of the project is to put the search for tractable algorithmic graph problems into a systematic and methodological framework: instead of focusing on specific sporadic problems, we intend to obtain a unified algorithmic understanding by mapping the entire complexity landscape of a particular problem domain. Completely classifying the complexity of each and every algorithmic problem appearing in a given formal framework would necessarily reveal every possible algorithmic insight relevant to the formal setting, with the potential of discovering novel algorithmic techniques of practical interest. This approach has been enormously successful in the complexity classifications of Constraint Satisfaction Problems (CSPs), but comparatively very little work has been done in the context of graphs. The systematic investigation of hard algorithmic graph problems deserves the same level of attention as the dichotomy program of CSPs, and graph problems have similarly rich complexity landscapes and unification results waiting to be discovered. The project will demonstrate that such a complete classification is feasible for a wide range of graph problems coming from areas such as finding patterns, routing, and survivable network design, and novel algorithmic results and new levels of algorithmic understanding can be achieved even for classic and well-studied problems.

In large distributed computing systems there is a big performance advantage when all communication can be carried out synchronously. Current synchronization techniques result in long communication latencies as the systems scale up in size and operating frequency. We identify two key application areas in which this is an immediate and pressing challenge. 1. Large Networks-on-Chip (NoCs) do not operate synchronously, despite the relative ease of design and low-latency communication this would offer. 2. Despite issues of security and availability, current cellphone networks rely on Global Navigation Satellite Systems (GNSS) such as GPS to obtain tightly synchronized time. We propose the application of Gradient Clock Synchronization (GCS) as a novel clock synchronization method for these applications. GCS minimizes the time offset between close-by parts of the system. This results in much smaller offsets between such parts than standard techniques that aim at minimizing the maximum global offset only. Given that in the above application settings, it is the offset between close-by parts that matters, this enables us to achieve large improvements in performance. In particular, we can eliminate the issues faced by NoC designs and cellphone networks that we pointed out above. The main objectives of the proposed PoC project itself can be stated as follows. - Development, fabrication, and evaluation of an ASIC demonstrator for SoC and NoC clocking. - Development and evaluation of a secure wireless implementation of the GCS algorithm. - Patent protection of the generated intellectual property. - Finding industrial pilot partners for development of products in follow-up projects.

Voltage droops are unpredicted drops in the supply voltage of computer chips, which often occur as a result of nearby bursts of high intensity circuit activity. This proposal is concerned with fast voltage droops, where voltage drops within a few clock cycles. This means that any dynamic response must take place within one or at most two clock cycles. A promising direction for combining the advantages of a stable reference clock with a small response time are mixed-signal control loops, in which voltage measurements are digitized and control decisions are taken by digital logic. However, digitally measuring a dynamically changing voltage may cause metastability of the sampling circuit. Conventional approaches employ synchronizers to make the probability of metastable upsets negligible, which costs 2-3 clock cycles of additional delay. Based on results of the ERC starting grant project "A Theory of Reliable Hardware,'' we provide a simple, compact circuit that guarantees the desired behavior without incurring synchronizer delay. This yields a practical method for adaptive response to fast droops, which bears the promise of increasing computational efficiency. Conservative estimates suggest performance improvements of at least 5%, which would be of substantial economical interest. The main obstacle to commercialization is a gap between theory and practice: Without an existing implementation, it takes a long time to develop a product and the associated risks are high. In this project, we will overcome this hurdle by developing, producing, and evaluating an Application-Specific Integrated Circuit (ASIC) demonstrator for our approach. We complement this primary goal by tasks aiming at maximizing impact: publication of results in high-profile scientific venues, patent protection to facilitate commercialization, and outreach to potential industry partners for developing products.

Cryptology is a foundation of information security in the digital world. Today's internet is protected by a form of cryptography based on complexity theoretic hardness assumptions. Ideally, they should be strong to ensure security and versatile to offer a wide range of functionalities and allow efficient implementations. However, these assumptions are largely untested and internet security could be built on sand. The main ambition of Almacrypt is to remedy this issue by challenging the assumptions through an advanced algorithmic analysis. In particular, this proposal questions the two pillars of public-key encryption: factoring and discrete logarithms. Recently, the PI contributed to show that in some cases, the discrete logarithm problem is considerably weaker than previously assumed. A main objective is to ponder the security of other cases of the discrete logarithm problem, including elliptic curves, and of factoring. We will study the generalization of the recent techniques and search for new algorithmic options with comparable or better efficiency. We will also study hardness assumptions based on codes and subset-sum, two candidates for post-quantum cryptography. We will consider the applicability of recent algorithmic and mathematical techniques to the resolution of the corresponding putative hard problems, refine the analysis of the algorithms and design new algorithm tools. Cryptology is not limited to the above assumptions: other hard problems have been proposed to aim at post-quantum security and/or to offer extra functionalities. Should the security of these other assumptions become critical, they would be added to Almacrypt's scope. They could also serve to demonstrate other applications of our algorithmic progress. In addition to its scientific goal, Almacrypt also aims at seeding a strengthened research community dedicated to algorithmic and mathematical cryptology. --