GENESIS, backed by Horizon Europe, aims to make semiconductor manufacturing sustainable, aligning with the European Green Deal, by minimizing environmental impact with eco-friendly innovations. [Objectives] GENESIS aims to replace harmful materials with safer options, improve waste management, and enhance the use and recyclability of scarce materials. [Innovations] GENESIS introduces innovations in three key areas: • Innovative materials: PFAS-free polymer and eco-friendly gas alternatives complying with EU regulations. • Waste & emissions monitoring: Cutting-edge sensors detect hazardous substances for efficient aqueous and gas waste elimination, reducing environmental and health risks. • Scarce material management: New integration technologies optimize material usage and initiate recycling of scarce materials like Gallium, Niobium, and silicon carbide. [Methodology] GENESIS employs four technical work packages to research sustainable material substitution, emission reduction, and resource management. This modular approach promotes scalability and integration with existing processes, fostering a circular economy in the semiconductor sector. Supervised by management work packages, it quantifies environmental efficiency and engages in dissemination to promote European technological achievements [Outcomes] The project targets a 50% cut in hazardous materials, 30% decrease in emissions and waste, and improved scarce material recyclability, boosting EU semiconductor sustainability and global competitiveness. [Impact] GENESIS supports EU's tech sovereignty and resilience through accurate monitoring and sustainable practices. It positions Europe as a leader in sustainable semiconductor tech, setting new standards for impact-oriented communication and dissemination.

New microelectronic applications such as wireless communications or radar detections require increasingly high data rates or resolutions. That implies to work at very high frequencies, in the millimetre waves domain. More specifically, in the frequency range 140-220 GHz (G-band), microelectronic circuits are emerging but suffer from a lack of complete characterization tools. There is a strong need for in wafer integrated measurement set-ups. Hence the BISCIG project aims to integrate, for the first time, a measurement system that would directly and completely measure incoming and outgoing powers, at all ports, and very close to the Device Under Test (DUT). The set-up is proposed in G-band. This project includes two versions. The first version (called "load-pull") concerns large signal power measurements to characterize power amplifiers in millimeter and sub-millimeter-wave bands. External current measurement devices, such as commercial impedance tuners, cannot do that efficiently. Because of their intrinsic losses in G-band, they cannot cover all the impedances of the complex plane to be presented at the output of the power amplifier. The second version will enable to characterize 4-ports DUT with small signal analysis (called “S-parameters”) and to perform differential measurements. Indeed, such instrument does not exist beyond 110 GHz. The BISCIG project therefore meets an industrial need for characterization of devices for new applications and expanding in G-band (high-speed communication systems, radar detection, imagers). Our solution consists in addressing the integrated measurement set-up with a well-known signal covering the 35-55 GHz spectrum. This microwave signal is then amplified and frequency quadrupled in order to address the G-band in the same technology as the DUT. Finally, we measure DC output signals as images of the detected powers, to characterize the behaviour of the DUT. The technology, provided by STMicroelectronics, is the SiGe BiCMOS 55 nm which is very powerful in the millimeter-wave band. The Back End of Line is very well suited to realize passive devices (thick metals in the upper layers). The Front End of Line is completely suitable as well for active devices (fT/fmax = 300/400 GHz). The academic partners will work closely, hand in hand, with the manufacturer STMicroelectronics providing the technology. IMEP-LAHC will design the measurement systems while IEMN will handle the characterization of the component blocks as well as the various sub- systems.

The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform. Additional developments will be performed for the integration of memory, power management, connectivity, hard security on the same chip. The project will also target the industrialization of the embedded Phase Change Memory (PCM) technology built on top of the FDSOI 28nm logic process pilot line. The development of the ePCM will be driven by the final application requirements as well as decreasing the power consumption. The alternative memory solutions will be also studied as they have different - and complementary - traits in such areas as read/write speed, power and energy consumption, retention and endurance, and device density and benchmarked with the ePCM and the conventional eFlash. Continued advances in materials, device physics, architectures and design could further reduce the energy consumption of these memories. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage. These activities encompass such developments as: technology enhancements for various specific application requirements such as wide temperature range and reliability, high security requests, high flexibility…, design enablment allowing first time silicon success, prototyping demonstrator products in the different application areas. In the WAKEMEUP project, new devices and systems will be developed by the application partners in automotive and secure based on FD-SOI and embedded digital technology to answer specific applications needs.

The 2001 “International Technology Roadmap for Semiconductors” (ITRS), which defines the specifications and objectives to be reached for the next generation components for the microelectronic industry, introduced for the first time a new criterion the “Line Edge Roughness (LER)” of the photolithography patterns. These patterns are produced with the help of photosensitive resins, a key processing step in the semiconductor manufacturing. The best microlithography resins allow today LER of the order of 5 to 7 nm. This microlithography pattern roughness limits the possibility to control accurately the length of the transistor gate increasing, thus, it’s leaking currents. The aim of this project is to understand the physical chemical mechanisms inducing the LER and optimize the synthesis and formulation of the photosensitive resins in order to reach acceptable values for this new criterion. This project presents a strong multidisciplinary character. Thanks to the partnership and complementarities between the teams of STMicroelectronics, Atomic Energy Agency, Laboratory of Polymer Engineering for High Technologies, Department of Photochemistry and Rohm and Haas Electronic Materials Corp. We will carry out this project starting from the synthesis of new polymer resins and their formulation with functional additives until the optimization of the photolithography processing step with tests and its integration to a manufacturing line for components of the future microelectronics.