The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7’s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

In line with industry needs, Moore’s law, scaling in ITRS 2013/2015, and ECSEL JU MASP 2016, the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module integration for the 5 nm node. This is planned with available EUV/NA0.33 scanners that are optimized for mix and match with existing DUV/NA1.35 scanners, and with system design and development of a new hyper NA EUV lithography tool to enable more single exposure patterning at 5 nm to create complex integrated circuits. Process steps for modules in Front-end, Middle and Back-end of line are discovered and developed using the most advanced tool capabilities and they are evaluated morphologically and electrically using a relaxed test vehicle. During the development, specific challenges in metrology are assessed and metrology tools are upgraded or newly developed. The results are demonstrated in the imec pilot line with qualified metrology tools at the 5 nm node. The TAKEMI5 project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets, as set out in the MASP, at a (disruptive) new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the module integration of electronic devices for the 5nm node in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary. The cost aware development process supports the involved companies, and places them in an enhanced position for their worldwide competition. Through their worldwide affiliations, the impact of the TAKEMI5 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.