The TAKE5 project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 10nm technology node and the ECSEL JU project SeNaTe aiming at the 7nm technology node. The main objective of the TAKE5 project is the demonstration of 5nm patterning in line with the industry needs and the ITRS roadmap in the Advanced Patterning Center at the imec pilot line using innovative design and technology co-optimization, layout and device architecture exploration, and comprising demonstration of a lithographic platform for EUV technology, advanced process and holistic metrology platforms and new materials. A lithography scanner will be developed based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules new materials will need to be introduced. Introduction of these new materials brings challenges for all involved deposition processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch steps will be studied. The project will be dedicated to find the best options for patterning. The project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary and covers all aspects of 5nm patterning development.

The objective of the 10Ce pThe objective of the 10Ce project is to explore and realize solutions for the 10 CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moores law alive. The 10Ce project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. Development of new computational lithography solutions to print 10 CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: Demonstrate a fully functional monolithic CFET (mCFET) Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10 3D CFET devices, interconnect and materials

Within the food chain of equipment delivery for the semiconductor industry, Europe has kept a very strong position in the metrology area with many companies establishing themselves as main leaders in the field. Hence in line with the objectives of the ICT25 call for innovation action to overcome the (initial) barriers for the successful commercialization of novel European products, this project aims at exploring for a number of metrology solutions their technological readiness, reliability and relevance of the developed protocols, and the COO. The portfolio within the project covers new metrology concepts addressing specifically the processing challenges linked to 3D-Devices and range from probing basic layer properties (composition, electrical properties) in FEOL to control of metallization in BEOL up to issues linked to die stacking. Due to the specific processing steps which need to be addressed, three separate metrology tools will be assessed in this project i.e a Tofsims system (IonTOF) with build-in Scanning Probe stage and FIB column for true 3D-composition profiling, a completely automated micro-Hall and sheet resistance measurement tool (Capres) with additional capabilities for measurements on dedicated test structures (prior to full BEOL) and an GHz acoustic Microscope (Tepla) for probing voids in TSV’s and stacked dies. As some of them (IonTOf, Capres) are addressing partly complementary information (composition versus electrical properties), their co-existence in this project creates additional value as beyond the tool assessment also a methodology based on combining these concepts can be explored and certified. Moreover a significant efficiency gain is created as they can employ similar test structures and devices. For each of these tools, the basic metrology concepts are existing and validated in the lab on selected applications but their general applicability field within the semiconductor industry still needs to be established

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7’s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.