CHORYS directly prioritises support for data-intensive applications in the context of the European Open Computing Architecture by developing and demonstrating open and programmable accelerators. Through CHORYS, we will demonstrate that European cloud providers and their customers can leverage open accelerators for near-data processing and asynchronous data services to improve the performance, energy-efficiency, and cost of data-intensive applications. This overall goal is aligned with the expected impact of the topic destination as CHORYS will contribute to the next steps of development and adoption of Open technologies. More specifically, we expect that CHORYS will contribute to Europe taking a leadership position in RISC-V based accelerators, with a workforce highly skilled in hardware/software co-design. The consortium is uniquely positioned to take up this challenge. Codasip, Europe’s leading RISC-V company with billions of chips shipped, will commercialize RISC-V IP licenses and Electronic Design Automation (EDA) software subscriptions, demonstrated in the projects’ open accelerators. Menta, the pioneer embedded FPGA (eFPGA) company, which is part of the European Processor Initiative, will contribute to the development of a European programmable storage controller. Cyso will extend the CHORYS demonstrators to deploy open and programmable accelerators in their high-performance public cloud platform, resulting in orders of magnitude net cost savings. The universities partners have track records of successful collaborations with recently published breakthrough results on hardware-software co-design, near-data processing, and asynchronous data services.

Space Market is liviSpace Market is living a mutation with the emergence of NewSpace, promoting integration/miniaturization, satellite acceleration, cost-efficient and cost-reduction approaches for all mission types: Earth Observation, Science, Telecom, Navigation and Robotic Exploration. Accordingly, middle range ASIC solutions are in competition with high performance/high capacity FPGA, new multicore devices and Rad Tolerant parts and COTS. Indeed, Mixed Signal ASIC solutions offer functional added value for testability of electronic units and digitalization of full analog functions. Hence, the PROMISE project sets clear and measurable objectives to optimize the design cost, shorten schedule and de-risk analog and mixed ASIC radhard design, manufacturing and qualification by covering the needs of the space industry. More specifically, PROMISE will provide the space community with a flexible mixed signal ASIC architecture design ecosystem built on a portfolio of hardened features. The project will also provide a flexible mixed signal ASIC manufacturing and qualification ecosystem. Last but not least, PROMISE will deliver IP dissemination, commercialization and intellectual property management to allow efficient reuse of the project’s outcomes and efficient environment for new IPs and mid-range ASIC design for space applications. PROMISE, led by Thales Alenia Space, encompasses diverse European partners, subcontractors, potential users or solution providers, all top actors of the European Mixed Signal ASIC ecosystem. The market for mega constellations is in full swing and several initiatives promoted by different operators are already underway. Thanks to PROMISE, a 50 % market share will be reached, so an estimate of 706 satellites will be delivered within a period of 5 years. Assuming only 1 PROMISE based ASIC per constellation and at least 4 pieces of this ASIC per satellite, this means more than 2800 units will be delivered in the first 5 years after the project.

The EPI SGA1 project will be the first phase of the European Processor Initiative FPA, whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications. EPI SGA1 will: - Develop the roadmap for the full length of the EPI initiative - Develop the first generation of technologies through a co-design approach (IPs for general-purpose HPC processors, for accelerators, for trusted chips, software stacks and boards) - Tape-out of the first generation chip by integrating the IPs developed - Validate this chip in the HPC context and in the automotive context using a demonstration platform The project will deliver a high performance, low power processor, implementing vector instructions and specific accelerators with high bandwidth memory access. The EPI processor will also meet high security and safety requirements. This will be achieved through intensive use of simulation, development of a complete software stack and tape-out in the most advanced semiconductor process node. SGA1 will provide a competitive chip that can effectively address the requirements of the HPC, AI, automotive and trusted IT infrastructure markets.

Today only very light AI processing tasks are executed in ubiquitous IoT endpoint devices, where sensor data are generated and access to energy is usually constrained. However, this approach is not scalable and results in high penalties in terms of security, privacy, cost, energy consumption, and latency as data need to travel from endpoint devices to remote processing systems such as data centres. Inefficiencies are especially evident in energy consumption. To keep up pace with the exponentially growing amount of data (e.g., video) and allow more advanced, accurate, safe and timely interactions with the surrounding environment, next-generation endpoint devices will need to run AI algorithms (e.g., computer vision) and other compute intense tasks with very low latency (i.e., units of ms or less) and energy envelops (i.e., tens of mW or less). NimbleAI will harness the latest advances in microelectronics and integrated circuit technology to create an integral neuromorphic sensing-processing solution to efficiently run accurate and diverse computer vision algorithms in resource- and area-constrained chips destined to endpoint devices. Biology will be a major source of inspiration in NimbleAI, especially with a focus to reproduce adaptivity and experience-induced plasticity that allow biological structures to continuously become more efficient in processing dynamic visual stimuli. NimbleAI is expected to allow significant improvements compared to state-of-the-art (e.g., commercially available neuromorphic chips), and at least 100x improvement in energy efficiency and 50x shorter latency compared to state-of-the-practice (e.g., CPU/GPU/NPU/TPUs processing frame-based video). NimbleAI will also take a holistic approach for ensuring safety and security at different architecture levels, including silicon level.