At the core of every electronic device, enabling a product to be connected to the Internet, is an embedded processor. IoT, AI, 5G, data encryption/decryption etc., they all rely on power-efficient, secure, and economical embedded processors to carry out their important on-chip functions. These technologies are changing everything about semiconductor industry. The speed is not what matters the most anymore. Energy consumption, durability, miniaturization and configurability are greatly important as these chips are being put into multitude of industries & plethora of applications. General-purpose chips just would not do it – they could handle each of tasks; however, they would be large and power inefficient. Thus the demand for custom chips keeps rising. The industry players will compete based on the best chip for specific purpose - what data capture & communications services their chips enable, at what cost. For companies failing to differentiate their products because they are using the same IP building blocks as their competitors and those with margins squeezed by legacy providers, Codasip offers a compelling value proposition: a processor IP with very high performance, very low power consumption, fully tailorable so that it can be made uniquely for each customer and application domain for convenient price. We created a broad portfolio of licensable RISC-V processors IP consisting of several RISC-V derivatives for a broad range of application requirements, from very small-footprint and low-gate-count cores, to high-performance, high-frequency cores with advanced DSP capabilities, suiting from wireless sensors to 5G and AI chips. We are the experts in processor design, holding the leading position in RISC-V processor IP. Key to our success are highly skilled people developing our solution, understanding emerging technologies and making us compete with the best of the best. Our commercial teams make us reach global markets, with customers as far as Japan or US.

CHORYS directly prioritises support for data-intensive applications in the context of the European Open Computing Architecture by developing and demonstrating open and programmable accelerators. Through CHORYS, we will demonstrate that European cloud providers and their customers can leverage open accelerators for near-data processing and asynchronous data services to improve the performance, energy-efficiency, and cost of data-intensive applications. This overall goal is aligned with the expected impact of the topic destination as CHORYS will contribute to the next steps of development and adoption of Open technologies. More specifically, we expect that CHORYS will contribute to Europe taking a leadership position in RISC-V based accelerators, with a workforce highly skilled in hardware/software co-design. The consortium is uniquely positioned to take up this challenge. Codasip, Europe’s leading RISC-V company with billions of chips shipped, will commercialize RISC-V IP licenses and Electronic Design Automation (EDA) software subscriptions, demonstrated in the projects’ open accelerators. Menta, the pioneer embedded FPGA (eFPGA) company, which is part of the European Processor Initiative, will contribute to the development of a European programmable storage controller. Cyso will extend the CHORYS demonstrators to deploy open and programmable accelerators in their high-performance public cloud platform, resulting in orders of magnitude net cost savings. The universities partners have track records of successful collaborations with recently published breakthrough results on hardware-software co-design, near-data processing, and asynchronous data services.

HPC Digital Autonomy with RISC-V in EurHPC Digital Autonomy with RISC-V in Europe (DARE) will address Europe’s deficit in digital autonomy for High Performance Computing and AI, by creating truly European products for European supercomputers for research and industry. The project builds upon the solid research foundation from EPI, EUPILOT, EUPEX, DEEP-SEA, eProcessor, MEEP and related projects, and it takes advantage of the open RISC-V ecosystem, chiplet revolution and open-source software. It is the first phase of the ambitious 6-year plan set out in the DARE FPA proposal, and it defines clear intra- and inter-phase SMART KPIs and success criteria, on the road to European digital autonomy while supporting current and future computing needs. We will develop and tape-out, in advanced technology, three RISC-V-based chiplets: a vector accelerator for high-precision HPC and emerging applications, an AI Processing Unit inference accelerator for HPC AI applications and an HPC-focused European general-purpose processor. These chiplets bring cost and yield advantages by going beyond the reticle size limitations imposed by monolithic chips and they will be integrated in a mix-and-match fashion to build specific systems. DARE uses a carefully selected set of the most significant European HPC and AI applications to drive hardware (HW) and software (SW) activities in a HW/SW co-design scheme, in order to ensure that the project’s HW and SW results meet the requirements of the European HPC and AI communities. It will build a complete SW stack, optimized for DARE HW, that supports these cutting-edge applications. To make rapid progress, SW and HW developments proceed in parallel, leveraging early access to RISC-V hardware emulation and simulation. Finally, the project will elaborate a detailed technical roadmap and pathfinding, defining the major steps and milestones to be followed in the next phase, in order to achieve the goal of next-generation post-exascale EU supercomputers.

TRISTAN’S overarching aim is to expand, mature and industrialize the European RISC-V ecosystem so that it is able to compete with existing commercial alternatives. This will be achieved by leveraging the Open-Source community to gain in productivity and quality. This goal will be achieved by defining a European strategy for RISC-V based designs including the creation of a repository of industrial quality building blocks to be used for SoC designs in different application domains (e.g. automotive, industrial, etc.). The TRISTAN approach is holistic, covering both electronic design automation tools (EDA) and the full software stack. The broad consortium will expose a large number of engineers to RISC-V technology, which will further encourage adoption. This ecosystem will ensure a European sovereign alternative to existing industrial players. The 3-year project fits in the strategy of the European Commission to support the digital transformation of all economic and societal sectors, and speed up the transition towards a green, climate neutral and digital Europe. This transformation includes the development of new semiconductor components, such as processors, as these are considered of key importance in retaining technological and digital sovereignty and build on significant prior investments in knowledge generation in this domain. Development strategies leveraging public research funding that exploit Open-Source have been shown to boost productivity, increase security, increase transparency, allow better interoperability, reduce cost to companies and consumers, and avoid vendor lock-ins. The TRISTAN consortium is composed of 46 partners from industry (both large industries as well as SMEs), research organizations, universities and RISC-V related industry associations, originating from Austria, Belgium, Finland, France, Germany, Israel, Italy, the Netherlands, Poland, Romania, Turkey and Switzerland.

Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. RISC-V ISA can be used for a wide variety of applications ranging from low power and low gate count embedded cores to advanced high frequency application cores. We are extending our portfolio of IP cores to include high-end high-performance compute area, complementing our cores that cover the power efficient embedded and mid range compute area: a new generation of advanced core with a 9-stage pipeline with out-of -order superscalar architecture called A90. The release of A90 will lead towards the A110 core with heavily speculative execution and an 11-stage pipeline. The design of these cores will simultaneously trigger a release of Codasip Studio processor design tool for high-end compute, including advanced features like support of out of order architectures.