The tremendous increase of transistors integration during the last few years has reached the limits of classic Von Neuman architectures. This has enabled a wide adoption of parallel processors by the industry, enabling many-core processing architectures as a natural trend for the next generation of computing devices. Nonetheless, one major issue of such massively parallel processors is the design and the deployment of applications that cannot make an optimal use of the available hardware resources. This limit is even more acute when we consider application domains where the system evolves under unknown and uncertain conditions such as mobile robotics, IoT, autonomous vehicles or drones. In the end, it is impossible to foresee every possible context that the system will face during its lifetime, making thus impossible to identify the optimal hardware substrate to be used. Interestingly enough, the biological brain has ”solved” this problem using a dedicated architecture and mechanisms that offer both adaptive and dynamic computations, namely, self-organization. However, even if neuro-biological systems have often been a source of inspiration for computer science (as recently demonstrated by the renewed interest in deep-learning), the transcription of self-organization at the hardware level is not straightforward and requires a number of challenges to be taken-up. The first challenge is to extend the usual self-organization mechanisms to account for the dual levels of computation and communication in a hardware neuromorphic architecture. From a biological point of view, this corresponds to a combination of the so-called synaptic and structural plasticities. We intend to define computational models able to simultaneously self-organize at both levels, and we want these models to be hardware-compliant, fault tolerant and scalable by means of a neuro-cellular structure. The second challenge is to prove the feasibility of a self-organizing hardware structure. Considering that these properties emerge from large scale and fully connected neural maps, we will focus on the definition of a self-organizing hardware architecture based on digital spiking neurons that offer hardware efficiency. The third challenge consists in coupling this new computation paradigm with an underlying conventional manycore architecture. This will require the specification of a Network-on-Chip that adapts to self-organizing hardware resources, as well as the definition of a programming model using the learning of input data to better and automatically divide and allocate functional elements. Hence, this project is a convergence point between past research approaches toward new computation paradigms: adaptive reconfigurable architecture, cellular computing, computational neuroscience, and neuromorphic hardware. 1. SOMA is an adaptive reconfigurable architecture to the extent that it will dynamically reorganize both its computation and its communication by adapting itself to the data to process. 2. SOMA is based on cellular computing since it targets a massively parallel, distributed and decentralized neuromorphic architecture. 3. SOMA is based on computational neuroscience since its self-organization capabilities are inspired from neural mechanisms. 4. SOMA is a neuromorphic hardware system since its organization emerges from the interactions between neural maps transposed into hardware from brain observation. This project represents a significant step toward the definition of a true fine-grained distributed, adaptive and decentralized neural computation framework. This new computing framework may indeed represent a viable integration of neuromorphic computing into the classical Von Neumann architecture and could endow these hardware systems with novel adaptive properties.