Performance analysis of multilayer interconnections for megabit static random access memory chip
Copyright policy )Performance analysis of multilayer interconnections for megabit static random access memory chip
Interconnections problems in the megabit static random access memory (SRAM) chip are studied. A multilayer interconnect capacitance model is developed, and effects of interconnection on SRAM device performance parameters, such as propagation delay, speed, power consumption, and noise characteristics, are analyzed. A case study of 1-Mb SRAM chip interconnection is discussed. A multilayer interconnect approach is proposed to overcome on-chip interconnection difficulties. By implementing a double-layer interconnect approach, the wire length and chip size were reduced to 69\% and 58\%, respectively. Maximum access time of 30.8 ns with 1 W at 100 deg;C and wafer yield as high as 10\% was achieved
- University of Montreal Canada
capacitance model, semiconductor device noise, static RAM, capacitance, chip size, Propagation delay, random access memory chip, Speed, power system interconnection, 30.8 ns, crosstalk, megabit SRAM, semiconductor device models, metallisation, access time, integrated circuit interconnections, multilayer interconnections, noise characteristics, 1 W, performance analysis, double-layer interconnect, wafer yield, Nonhomogeneous media, 1 Mbit, delays, performance parameters, power consumption, Random access memory, CMOS integrated circuits, Energy consumption, wire length, SRAM chips
capacitance model, semiconductor device noise, static RAM, capacitance, chip size, Propagation delay, random access memory chip, Speed, power system interconnection, 30.8 ns, crosstalk, megabit SRAM, semiconductor device models, metallisation, access time, integrated circuit interconnections, multilayer interconnections, noise characteristics, 1 W, performance analysis, double-layer interconnect, wafer yield, Nonhomogeneous media, 1 Mbit, delays, performance parameters, power consumption, Random access memory, CMOS integrated circuits, Energy consumption, wire length, SRAM chips
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