Intrinsic stresses in bondpads may lead to early failure of IC's. In order to determine the intrinsic stresses in semiconductor structures, a new procedure is set up. This procedure is a combined experimental/numerical approach which consists of the following steps: First, a conductive gold layer (20 nm thickness) is deposited on the power line surface; subsequently markers (small holes) for Digital Image Correlation (DIC) purposes are added using a focused ion beam (FIB). Next, a scanning electron microscope (SEM) is used to image the original ('before') surface. The FIB is then used to mill a slot into the surface to release the intrinsic stresses, which results in contraction of the surface. Finally, a SEM image is made of the contracted ('after') surface. DIC is used to determine in-plane displacements due to FIB milling. DIC performance was verified by the traditional strain gauge approach. An inverse Finite Element (FE) modelling approach is used to determine the before mentioned stresses. The slot displacements found with DIC are inserted into an FE model of the product. Stresses which now emerge from closing the (virtual) FIB slot correspond to the intrinsic stresses which were originally present in the product. Favorable positions for FIB milling are near the edge of the structure and displacements are determined to be in the nanometer range. This indicates a presence of substantial (50-250 MPa) compressive stresses. Displacements near the center of the structure appear to be smaller than DIC resolution. ©2010 IEEE.