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Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas

descriptionPublicationkeyboard_double_arrow_right Article , Journal 01 Dec 2016 Spain Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Electron Devices, volume 63, pages 5,012-5,020 (issn: 0018-9383, eissn: 1557-9646,

Authors: Juan Nunez; Maria J. Avedillo;

doi: 10.1109/ted.2016.2616891

handle: 10261/155915

Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas

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Abstract

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. Peer reviewed

Country

Spain

Related Organizations

Spanish National Research Council
Spain
University of Seville
Spain
Seville Institute of Microelectronics
Spain

Keywords

Energy efficiency, Low supply voltage, Low power, Tunnel transistors, Steep subthreshold slope, Energy efficieny

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