This paper presents the design and implementation of a second-order switched-current (SI) sigma-delta (Σ-Δ) modulator (SDM) used in motor control system. To complete this technique, a current-mode sample-and-hold circuit is proposed. It consists of a feedback circuit to reduce the impedance at the input and a common-mode feedforward (CMFF) circuit to improve the common-mode offset at the output. Furthermore, a coupled differential (CDR) feedback memory cell (FMC) is used with CMFF SI memory cell to eliminate the clock feedthrough (CFT) error considerably. All the proposed circuits establish the second-order sigma-delta modulator and simulate with the parameters of the TSMC 0.35μm CMOS process technology. The simulation results reveal that the maximum signal to noise plus distortion ratio (SNDR) is about 87 dB, which is equal to 14 bits resolution, within the conditions that the sampling rate is a value of 5.12MHz and the oversampling ratio is 256. Note that the power dissipation is about 11mW, which is considerably low.