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Untethered robots carry their own power supply in the form of a battery pack, which has a crucial impact on the robot’s performance. Although battery technologies are richly studied and optimized for applications such as electric vehicles, computers and smartphones, they are often a mere afterthought in the design process of a robot system. This tutorial paper proposes criteria to evaluate the suitability of different battery technologies for robotic applications. Taking into consideration the requirements of different applications, the capabilities of relevant battery technologies are evaluated and compared. The tutorial also discusses current limitations and new technological developments, pointing out opportunities for interdisciplinary research between the battery technology and robotics communities.

AbstractOne of the main driving forces to lower the silicon solar cell modules overall cost is to decrease the thickness of the silicon substrate and, at same time, to reduce the material losses caused by the sawing of the silicon ingot. For this reason, a considerable number of methods have been proposed in the last decade to manufacture thin silicon foils which aim to replace the commonly used sawing technique. One of these methods is based on peeling off a thin layer from a silicon substrate by means of the residual stress induced either through the only deposition of a layer on a silicon substrate or through a succeeding thermal cycle of such a bilayer. Up to now, three different materials have been successfully employed in this technique: Nickel, Nickel/Chromium alloy and a Silver/Aluminium system. In this work we demonstrate the possibility to induce the lift-off of a thin silicon foil by means of curing an epoxy layer on top of a silicon wafer. This new method has the advantages of reducing metal contamination in the silicon and lowers the operating temperatures below 150°C.

The investigation of degradation of seven distinct sets (with a number of individual cells of n $ 12) of state of the art organic photovoltaic devices prepared by leading research laboratories with a combination of imaging methods is reported. All devices have been shipped to and degraded at Risø DTU up to 1830 hours in accordance with established ISOS-3 protocols under defined illumination conditions. Imaging of device function at different stages of degradation was performed by laser-beam induced current (LBIC) scanning; luminescence imaging, specifically photoluminescence (PLI) and electroluminescence (ELI); as well as by lock-in thermography (LIT). Each of the imaging techniques exhibits its specific advantages with respect to sensing certain degradation features, which will be compared and discussed here in detail. As a consequence, a combination of several imaging techniques yields very conclusive information about the degradation processes controlling device function. The large variety of device architectures in turn enables valuable progress in the proper interpretation of imaging results—hence revealing the benefits of this large scale cooperation in making a step forward in the understanding of organic solar cell aging and its interpretation by state-of-the-art imaging methods.

AbstractIn this paper we want to share our efforts on how to translate our high-quality epitaxial foils (epifoils) into cell-level performance. After framing our motivation in the introduction, we elaborate our approach at imec using available background on this topic and expected challenges. After presenting our method, consisting of layout, buildup and processing sequence, we share and compare our findings, discuss our characterization methods and add some basic simulations to improve our understanding.In conclusion, we demonstrated how we could process epitaxial foils into cells, using a completely low-temperature process and keeping the foils attached to a carrier (parent wafer for the frontside, superstrate glass for the rear side) all the way through. Even though there is room for improvement on several aspects (both electrical and optical), in a first attempt this cell integration already resulted in a best open-circuit voltage (Voc) of 695mV. Based on the loss analysis, the most promising improvements and their potential impact are pointed out.

This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE’s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system. This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876925, from MCIN/AEI/10.13039/501100011033 (grants PID2019-105660RB-C21 and PID2019-107255GB-C22), and from Aragon Government (T58_23R research group). Peer Reviewed